As device dimensions are downscaled, the introduction of high-k dielectric processes causes new challenging issues, for example, the depletion of poly silicon gates. A metal gate process is thus developed to eliminate the poly-gate depletion problem.
As is known in the art, after the formation of source/drain regions, an activation process is needed to activate source/drain regions and gate electrodes. The activation process is typically performed with an annealing step. Recently, annealing methods that require very short periods of time have been increasingly used due to their low thermal budgets. These annealing methods include laser annealing, flash annealing, and the like, in which the wafer is exposed to a high-energy light source for a very short time, for example, several milliseconds or less. During the annealing, the light energy is absorbed by the wafer, so that the wafer temperature is rapidly increased to, for example, 1000° C. or higher. Source/drain regions and gate electrodes are thus activated.
The escalation of the wafer temperature is dependent upon the light-absorbing abilities of the features on the surface of the wafer. It has been found that metal gates have a high reflection rate to lights commonly used in the activation process, and thus the introduction of metal gates into the CMOS process impacts the activation process. Accordingly, light absorption significantly depends on pattern density, leading to significant temperature variations from one region of a wafer to another, and from one wafer to another if the wafers are for different products.
Accordingly, what is needed in the art is a method for reducing the temperature variations in the annealing process and to reduce and/or eliminate the effects of pattern density on temperature uniformity.